1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
In recent years, there is an increased demand for nonvolatile semiconductor memory devices, such as EEPROMs. A nonvolatile semiconductor memory device has problems in that where adjacent ones of memory cells in the word-line direction are close to each other, the capacitive coupling between the adjacent floating gates inevitably increases.
To solve this problem, a depression is formed in an isolation insulating film between memory cells, and a control gate line (word line) is formed in the depression (which is disclosed, for example in Jpn. Pat. Appln. KOKAI Publication No. 2001-168306). A method for providing such a structure will be described, referring to FIGS. 13–15.
In FIG. 13, reference numeral 101 denotes a semiconductor substrate comprising an isolation trench 103 and an element-forming region 102. Numeral 104 denotes an isolation insulating film, numeral 105 denotes a lower gate insulating film (a tunnel insulating film), and numerals 106a and 106b denote polysilicon films serving as a floating gate. In the process illustrated in FIG. 13, the isolation insulating film 104 and polysilicon film 106a are overlaid with polysilicon film 106b, and a silicon oxide film 111 is formed on polysilicon film 106b. After the silicon oxide film 111 is patterned by lithography and etching, a film used for preparing side spacers is formed on the entire surface of the resultant structure. The film is etched by RIE or the like in such a manner that side spacers 112 are left on the side surfaces of the silicon oxide film 111. In this manner, the silicon oxide film 111 and the side spacers 112 define an etching mask having an opening portion 113.
Next, the polysilicon film 106b and the isolation insulating film 104 are etched, using the above-mentioned etching mask. As a result, a hollow portion 114 is defined, as shown in FIG. 14.
As shown in FIG. 15, the etching mask is removed, an upper gate insulating film (an ONO film) 107 is formed, and a polysilicon film 108a and a WSi film 108b, serving as control gate lines, are formed. Subsequently, the WSi film 108b, the polysilicon film 108a, the upper gate insulating film 107, the polysilicon films 106b and 106a, are patterned for isolation of memory cells.
In the prior art described above, the capacitive coupling between the adjacent floating gates (namely, the polysilicon films 106a and 106b) can be suppressed by filling the hollow portion 114 of the isolation insulating film 104 with the polysilicon film 108a. 
However, since lithography is used for patterning the silicon oxide film 111 in the prior art described above, there may be an alignment error between the pattern of the silicon oxide film 111 and the pattern of the isolation trench 103 (the isolation insulating film 104). In order to form the hollow portion 114 reliably in the isolation insulating film 104, the width of the etching mask composed of the silicon oxide film 111 and the side spacers 112 must be provided with a margin. In other words, the width of the opening portion 113 of the etching mask must be less than the width of the isolation trench 103 by the dimension corresponding to the margin. As a result, the width of the hollow portion 114, which is formed by etching the polysilicon film 106b and the isolation insulating film 104, is naturally less than the width of the isolation trench 103. Where the adjacent memory cells are arranged at short intervals (in other words, the isolation trench 103 is narrow), it is very difficult to fill the hollow portion 114 with the polysilicon film 108a. Hence, the capacitive coupling between floating gates is hard to suppress.
As described above, the prior art has problems in that if the isolation trench has a reduced width, a control gate line cannot be easily formed in the hollow portion 114 of the isolation insulating film, and the capacitive coupling between floating gates is hard to suppress.